1. Field of the Invention
This invention relates to the manufacture of semi-conductor memory devices and more particularly to a method of manufacture of vertical FET devices formed in trenches in a semiconductor substrate and the devices formed thereby.
2. Description of Related Art
Some background information is as follows:
1. It necessary to employ process steps which are different from conventional processes to scale down for deep sub-micron devices. PA1 2. There is an issue of compatibility in embedded flash memory devices. PA1 3. There has been low drain current in the past. PA1 1. Use vertical channel and drain/source structure to reduce cell area substantially. PA1 2. Use trench floating polysilicon method to planarize front gate topography in a way which is fully compatible with logic manufacturing process. PA1 3. Increase drain current by providing a large conductive width of the structure. PA1 1. An area scale down is more possible than in the past. PA1 2. Gate patterning and planarization are very compatible with the logic circuit manufacturing process. PA1 3. High drain current is available during programming and reading.
U.S. Pat. No. 5,108,938 of Solomon for "Method of Making a Trench Gate Complimentary Metal Oxide Semiconductor Transistor" shows a FET (Field Effect Transistor) with the source (S) and drain (D) regions on the substrate surface separated by a trench.
U.S. Pat. No. 5,391,506 of Tada et al. for "Manufacturing Method for Semiconductor Devices with Source/Drain Formed in Substrate Projection" shows a method for manufacturing semiconductor devices with source/drain regions formed in a substrate projection. A projection is formed in a substrate by anisotropic etching and a transistor is contained in the projection. The central portion of the projection covered with a gate electrode is formed as a channel region, and drain/source regions are formed on both sides of the projection by oblique ion implantation with the gate electrode as a mask.
U.S. Pat. No. 5,312,767 of Shimizu et al. for "MOS Type Field Effect Transistor and Manufacturing Method Thereof" shows a vertical SOI (Silicon On Insulator) transistor that has the S and D regions on opposite ends of a trench. However the device is not a Flash memory device.
U.S. Pat. No. 5,229,310 of Sivan "Method of Making a Self-Aligned Vertical Thin-Film Transistor in a Semiconductor Device" shows an EEPROM with a vertical orientation in a trench.
See Woo et al. U.S. Pat. No. 5,210,047 for "Process for Fabricating a Flash EPROM Having Reduced Cell Size".